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# Comparison of Cortex-M Architectures
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*Most information here taken from https://en.wikipedia.org/wiki/ARM_Cortex-M*
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## M0
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- **ARM Architecture Version**: ARMv6-M
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- **Pipeline**: 3-Stage
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- **Comp Arch**: von Neumann
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- Optimised for physical silicon die size + cost
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- Supports Thumb-1 and some of Thumb-2
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## M0+
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- **ARM Architecture Version**: ARMv6-M
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- **Pipeline**: 2-Stage
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- **Comp Arch**: von Neumann
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- Superset of M0
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- Optional MTB (micro trace buffer)
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- Optional MPU (memory protection unit)
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## M1
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- **ARM Architecture Version**: ARMv6-M
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- **Pipeline**: 3-Stage
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- **Comp Arch**: von Neumann
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- Optimized core especially designed to be loaded into FPGA chips.
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## M3
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- **ARM Architecture Version**: ARMv7-M
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- **Pipeline**: 3-Stage + branch speculation
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- **Comp Arch**: Harvard
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- All Thumb instructions
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- H/W divide
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- Saturation arithmetic
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- Optional MPU (memory protection unit)
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## M4
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- **ARM Architecture Version**: ARMv7E-M
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- **Pipeline**: 3-Stage + branch speculation
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- **Comp Arch**: Harvard
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- Essentially M3 + DSP
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- DSP: MAC + SIMD
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- Optional FPU
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- Optional MPU (memory protection unit)
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## M7
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- **ARM Architecture Version**: ARMv7E-M
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- **Pipeline**: 6-Stage + branch speculation
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- **Comp Arch**: Harvard
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- High performance, ~2x efficiency of M4
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- Superscaler
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- 64-Bit Instruction + Data buses
  
  

Verzia zo dňa a času 10:16, 7. august 2023

Všeobecné informácie


  1. Comparison of Cortex-M Architectures
    1. M0

- **ARM Architecture Version**: ARMv6-M - **Pipeline**: 3-Stage - **Comp Arch**: von Neumann - Optimised for physical silicon die size + cost - Supports Thumb-1 and some of Thumb-2

    1. M0+

- **ARM Architecture Version**: ARMv6-M - **Pipeline**: 2-Stage - **Comp Arch**: von Neumann - Superset of M0 - Optional MTB (micro trace buffer) - Optional MPU (memory protection unit)

    1. M1

- **ARM Architecture Version**: ARMv6-M - **Pipeline**: 3-Stage - **Comp Arch**: von Neumann - Optimized core especially designed to be loaded into FPGA chips.

    1. M3

- **ARM Architecture Version**: ARMv7-M - **Pipeline**: 3-Stage + branch speculation - **Comp Arch**: Harvard - All Thumb instructions - H/W divide - Saturation arithmetic - Optional MPU (memory protection unit)

    1. M4

- **ARM Architecture Version**: ARMv7E-M - **Pipeline**: 3-Stage + branch speculation - **Comp Arch**: Harvard - Essentially M3 + DSP - DSP: MAC + SIMD - Optional FPU - Optional MPU (memory protection unit)

    1. M7

- **ARM Architecture Version**: ARMv7E-M - **Pipeline**: 6-Stage + branch speculation - **Comp Arch**: Harvard - High performance, ~2x efficiency of M4 - Superscaler - 64-Bit Instruction + Data buses


Vysvetlivky:

  • (m) - Matlab / Simulink Support Package Available
  • (M) - Matlab / Simulink Support Package Available and Tested
  • (-S) zatial neexistuje podpora pre Simulink
  • (mbed) - mbedOS available (v2 - version 2), (v5, v6) verzia
  • (+A,a) - Arduino programming possible, tested/not tested

mbedOS

Procesory Nordic Semiconductor


Procesory NXP

Rozličné FRDM dosky, doplň prehľad

  • FRDM KL-25Z (M),(mbed) - Cortex M0+


Procesory STM32

Marking: 

STM	Manufacturer (STMicroelectronics) 	—-
32     32-bit MCU 	                        —- 
 F     Type of MCU 	                        F: Mainstream, L: Low power, H: High Performance, W: Wireless, C: Cost effective
 1	ARM Core Type 	                        0: M0, 1: M3, 2: M3, 3: M4, 4: M4, 7: M7
03     Line of MCU 	                        Details about speed, peripherals, Silicon Process, etc.
 C     No. of Pins 	                        F: 20, G: 28, K: 32, T: 36, S: 44, C: 48, R: 64,66, V: 100, Z: 144, I: 176
 8     Flash Size 	                        4: 16, 6: 32, 8: 64, B: 128, C: 256, D: 384, E: 512, F: 768, G: 1024, H: 1536, I: 2048 KB
 T     Package 	                        P: TSOOP, H: BGA, U: VFQFPN, T: LQFP, Y: WLCSP
 6     Temperature Range 	                6: -40°C to 85°C, 7: -40°C to 105°C

Programovanie:

Courses:

Zdroj: „https://senzor.robotika.sk/sensorwiki/index.php?title=Procesory_ARM&oldid=14849“