Procesory ARM: Rozdiel medzi revíziami
Z SensorWiki
Riadok 5: | Riadok 5: | ||
− | + | == Comparison of Cortex-M Architectures == | |
*Most information here taken from https://en.wikipedia.org/wiki/ARM_Cortex-M* | *Most information here taken from https://en.wikipedia.org/wiki/ARM_Cortex-M* | ||
+ | |||
+ | {| class="wikitable" style="text-align:center;" | ||
+ | |- style="font-weight:bold;" | ||
+ | ! style="font-weight:normal; text-align:left;" | | ||
+ | ! style="background-color:#ffffc7; color:#329a9d;" | M0 | ||
+ | ! style="background-color:#ffffc7; color:#329a9d;" | M0+ | ||
+ | ! style="background-color:#ffffc7; color:#329a9d;" | M1 | ||
+ | ! style="background-color:#ffffc7; color:#329a9d;" | M3 | ||
+ | ! style="background-color:#ffffc7; color:#329a9d;" | M4 | ||
+ | ! style="background-color:#ffffc7; color:#329a9d;" | M7 | ||
+ | |- | ||
+ | | style="font-weight:bold; text-align:left;" | ARM Architecture | ||
+ | | ARMv6-M | ||
+ | | ARMv6-M | ||
+ | | ARMv6-M | ||
+ | | ARMv7-M | ||
+ | | ARMv7E-M | ||
+ | | ARMv7E-M | ||
+ | |- | ||
+ | | style="font-weight:bold;" | Pipeline | ||
+ | | 3-Stage | ||
+ | | 2-Stage | ||
+ | | 3-Stage | ||
+ | | 3-Stage <br />+ branch speculation | ||
+ | | 3-Stage <br />+ branch speculation | ||
+ | | 6-Stage <br />+ branch speculation | ||
+ | |- | ||
+ | | style="font-weight:bold;" | Architecture | ||
+ | | von Neumann | ||
+ | | von Neumann | ||
+ | | von Neumann | ||
+ | | Harvard | ||
+ | | Harvard | ||
+ | | Harvard | ||
+ | |- | ||
+ | | style="font-weight:bold;" | Functions: | ||
+ | | Optimised for <br />physical silicon <br />die size + cost | ||
+ | | Superset of M0 | ||
+ | | Optimized core<br />designed to be loaded <br />into FPGA chips. | ||
+ | | All Thumb <br />instructions | ||
+ | | Essentially M3 + DSP | ||
+ | | High performance, <br />~2x efficiency of M4 | ||
+ | |- | ||
+ | | style="text-align:left;" | | ||
+ | | Supports Thumb-1 <br />and some of Thumb-2 | ||
+ | | Optional MTB <br />(micro trace buffer) | ||
+ | | | ||
+ | | H/W divide | ||
+ | | DSP: MAC + SIMD | ||
+ | | Superscaler | ||
+ | |- | ||
+ | | style="text-align:left;" | | ||
+ | | | ||
+ | | Optional MPU <br />(memory protection unit) | ||
+ | | | ||
+ | | Saturation arithmetic | ||
+ | | Optional FPU | ||
+ | | 64-Bit Instruction <br />+ Data buses | ||
+ | |- style="text-align:left;" | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | | ||
+ | | style="text-align:center;" | Optional MPU <br />(memory protection unit) | ||
+ | | style="text-align:center;" | Optional MPU <br />(memory protection unit) | ||
+ | | | ||
+ | |} | ||
## M0 | ## M0 | ||
− | + | ARM Architecture Version ARMv6-M | |
- **Pipeline**: 3-Stage | - **Pipeline**: 3-Stage | ||
- **Comp Arch**: von Neumann | - **Comp Arch**: von Neumann |
Verzia zo dňa a času 10:29, 7. august 2023
Všeobecné informácie
Obsah
Comparison of Cortex-M Architectures
- Most information here taken from https://en.wikipedia.org/wiki/ARM_Cortex-M*
M0 | M0+ | M1 | M3 | M4 | M7 | |
---|---|---|---|---|---|---|
ARM Architecture | ARMv6-M | ARMv6-M | ARMv6-M | ARMv7-M | ARMv7E-M | ARMv7E-M |
Pipeline | 3-Stage | 2-Stage | 3-Stage | 3-Stage + branch speculation |
3-Stage + branch speculation |
6-Stage + branch speculation |
Architecture | von Neumann | von Neumann | von Neumann | Harvard | Harvard | Harvard |
Functions: | Optimised for physical silicon die size + cost |
Superset of M0 | Optimized core designed to be loaded into FPGA chips. |
All Thumb instructions |
Essentially M3 + DSP | High performance, ~2x efficiency of M4 |
Supports Thumb-1 and some of Thumb-2 |
Optional MTB (micro trace buffer) |
H/W divide | DSP: MAC + SIMD | Superscaler | ||
Optional MPU (memory protection unit) |
Saturation arithmetic | Optional FPU | 64-Bit Instruction + Data buses | |||
Optional MPU (memory protection unit) |
Optional MPU (memory protection unit) |
- M0
ARM Architecture Version ARMv6-M
- **Pipeline**: 3-Stage - **Comp Arch**: von Neumann - Optimised for physical silicon die size + cost - Supports Thumb-1 and some of Thumb-2
- M0+
- **ARM Architecture Version**: ARMv6-M - **Pipeline**: 2-Stage - **Comp Arch**: von Neumann - Superset of M0 - Optional MTB (micro trace buffer) - Optional MPU (memory protection unit)
- M1
- **ARM Architecture Version**: ARMv6-M - **Pipeline**: 3-Stage - **Comp Arch**: von Neumann - Optimized core especially designed to be loaded into FPGA chips.
- M3
- **ARM Architecture Version**: ARMv7-M - **Pipeline**: 3-Stage + branch speculation - **Comp Arch**: Harvard - All Thumb instructions - H/W divide - Saturation arithmetic - Optional MPU (memory protection unit)
- M4
- **ARM Architecture Version**: ARMv7E-M - **Pipeline**: 3-Stage + branch speculation - **Comp Arch**: Harvard - Essentially M3 + DSP - DSP: MAC + SIMD - Optional FPU - Optional MPU (memory protection unit)
- M7
- **ARM Architecture Version**: ARMv7E-M - **Pipeline**: 6-Stage + branch speculation - **Comp Arch**: Harvard - High performance, ~2x efficiency of M4 - Superscaler - 64-Bit Instruction + Data buses
Vysvetlivky:
- (m) - Matlab / Simulink Support Package Available
- (M) - Matlab / Simulink Support Package Available and Tested
- (-S) zatial neexistuje podpora pre Simulink
- (mbed) - mbedOS available (v2 - version 2), (v5, v6) verzia
- (+A,a) - Arduino programming possible, tested/not tested
mbedOS
- Samostatná stránka Mbed OS
- API pozri dokumentáciu tu https://os.mbed.com/docs/mbed-os/v6.16/apis/i-o-apis.html
Procesory Nordic Semiconductor
- micro:bit (M),(mbed2),(A)
- nRF51822 - Cortex M0 (microbot v1.3 a 1.5)
- nRF52833 - Cortex M4 (microbit v2)
- Attila Hriňa: Procesory ARM. Bc. práca FEI STU 2023
- Pozri aj Mbed OS s vzorovymi programami
- Simulink: https://www.mathworks.com/help/supportpkg/microbit/ alebo aj https://www.mathworks.com/academia/courseware/microbit.html
- Simulink: https://www.mathworks.com/matlabcentral/fileexchange/61738-simulink-lessons-and-examples-for-bbc-micro-bit?status=SUCCESS
- Arduino Nano 33 BLE Sense
- nRF52840 - Cortex M4
Procesory NXP
Rozličné FRDM dosky, doplň prehľad
- FRDM KL-25Z (M),(mbed) - Cortex M0+
Procesory STM32
Marking:
STM Manufacturer (STMicroelectronics) —- 32 32-bit MCU —- F Type of MCU F: Mainstream, L: Low power, H: High Performance, W: Wireless, C: Cost effective 1 ARM Core Type 0: M0, 1: M3, 2: M3, 3: M4, 4: M4, 7: M7 03 Line of MCU Details about speed, peripherals, Silicon Process, etc. C No. of Pins F: 20, G: 28, K: 32, T: 36, S: 44, C: 48, R: 64,66, V: 100, Z: 144, I: 176 8 Flash Size 4: 16, 6: 32, 8: 64, B: 128, C: 256, D: 384, E: 512, F: 768, G: 1024, H: 1536, I: 2048 KB T Package P: TSOOP, H: BGA, U: VFQFPN, T: LQFP, Y: WLCSP 6 Temperature Range 6: -40°C to 85°C, 7: -40°C to 105°C
Programovanie:
- 0 Bare Bone
- 1 CMSIS
- 1 STM LL
- 2 HAL (CubeMX)
- 2 libopencm - https://github.com/libopencm3/libopencm3-miniblink/blob/master/template_stm32.c
- 3 API napr. mbedOS
- 3 Arduino https://github.com/stm32duino
- 4 Simulink https://github.com/ATM-HSW/mbed_target
Courses:
- Pill
- Blue Pill STM32F103C8T6 (a) (Cortex M3 @72 MHz, vrátane klonu CKS32F103C8T6 z Techfun.SK)
- CMSIS priklady tu: https://github.com/sandynomike?tab=repositories
- mbedOS https://os.mbed.com/users/hudakz/code/mbed-os-bluepill/
- Blue Pill STM32F103C8T6 (a) (Cortex M3 @72 MHz, vrátane klonu CKS32F103C8T6 z Techfun.SK)
- Black Pill STM32F411CEU6 (a) (Cortex M4 @100 MHz, aj z Techfun.SK
- Priklady od bare bone po HAL: https://www.codeinsideout.com/blog/stm32/blink/
- CMSIS tu https://mcturra2000.wordpress.com/2021/11/18/using-cmsis-and-systick-to-blink-an-led-on-an-stm32f4/
- BareBone tu https://github.com/lowbyteproductions/bare-metal-series/ (GCC and libopencm3)
- Black Pill STM32F411CEU6 (a) (Cortex M4 @100 MHz, aj z Techfun.SK
- Nucleo boards
- STM32C031C6T6 (mbed?)(-S)(+A) - najmenší 32-bitový procesor, cenovo ako náhrada za 8-bitové (2023)
- Web:
- YouTube MOOC course: https://www.youtube.com/playlist?list=PLnMKNibPkDnG_5q6DLNTMSBo5V24VXUDn
- Potom rozširujúce príklady tu https://github.com/STMicroelectronics/STM32CubeC0
- STM32L073RZT6 Cortex M0+ @32 MHz (-S)(+A)
- mbed: https://os.mbed.com/platforms/ST-Nucleo-L073RZ/
- Vojtěch Skřivánek: Programujeme STM32: zdolejte jednočipy profesionálů, TZ-one, 2022.
- Vojtěch Skřivánek: Programujeme STM32: bez knihoven, TZ-one, 2022.
- Vojtěch Skřivánek: Používáme FreeRTOS na mikrokontroleru STM32, TZ-one, 2023.
- STM32C031C6T6 (mbed?)(-S)(+A) - najmenší 32-bitový procesor, cenovo ako náhrada za 8-bitové (2023)